Commit graph

240 commits

Author SHA1 Message Date
MITSUNARI Shigeo
646da97503 use opModR2 for rdrand, rdseed, movq 2023-11-06 11:29:05 +09:00
MITSUNARI Shigeo
ccad6cecd1 use opModR2 for movdq2q, movq2dq 2023-11-06 11:24:22 +09:00
MITSUNARI Shigeo
3c21754b9c use opModR2 for movd, movmskps 2023-11-06 11:22:48 +09:00
MITSUNARI Shigeo
4718643ef5 use opModR2 for bswap, maskmovq, pmovmskb 2023-11-06 11:17:30 +09:00
MITSUNARI Shigeo
e1a1487072 try to use opModR2 2023-11-06 11:00:10 +09:00
MITSUNARI Shigeo
87b8c8ed25 adox passes the test 2023-11-01 18:18:52 +09:00
MITSUNARI Shigeo
6b19515ebd add adcx, adox with APX 2023-11-01 12:34:48 +09:00
MITSUNARI Shigeo
ea9cd9adea tweak 2023-10-30 16:03:32 +09:00
MITSUNARI Shigeo
8f49739da9 remove cmp of 3-op 2023-10-27 13:11:56 +09:00
MITSUNARI Shigeo
8d524b4a42 add op(r, r/m, imm) and op(r, r/m, r/m) 2023-10-27 10:52:26 +09:00
MITSUNARI Shigeo
acd7971392 use opModM instead of opMIB 2023-10-13 16:05:25 +09:00
MITSUNARI Shigeo
dd66cfb764 add tests of avx-vnni-int{8,16} 2023-08-07 10:59:12 +09:00
MITSUNARI Shigeo
e1c4c360b7 add SM4 2023-08-07 09:42:16 +09:00
MITSUNARI Shigeo
48f8dbeb63 add SM3 2023-08-07 09:27:33 +09:00
MITSUNARI Shigeo
5473d39330 vsha512* check regs 2023-08-07 08:59:14 +09:00
MITSUNARI Shigeo
5762819de3 add vsha512{msg1, msg2, rnds2} 2023-08-04 17:45:50 +09:00
MITSUNARI Shigeo
ad178a2196 add xabort/xbegin/xend 2023-08-02 09:42:22 +09:00
MITSUNARI Shigeo
2c59c5c91e add alias of vpclmulqdq 2023-07-05 17:40:36 +09:00
MITSUNARI Shigeo
729ae4aa37 fix alias of pclmulqdq 2023-07-05 17:34:36 +09:00
MITSUNARI Shigeo
ad0dfffd29 add senduipi/stui/testui/uiret 2023-02-20 14:07:43 +09:00
MITSUNARI Shigeo
e78f1121b9 add clui 2023-02-20 14:07:43 +09:00
MITSUNARI Shigeo
bef70d9b1b add prefetchit{0,1} 2022-12-07 16:16:58 +09:00
MITSUNARI Shigeo
c9347907d4 add CMPccXADD 2022-11-30 13:20:44 +09:00
MITSUNARI Shigeo
0f2f1aaa65 support rio-int 2022-11-25 17:31:34 +09:00
MITSUNARI Shigeo
3b0a19c418 vpmadd52{h,l}uq for avx-ifma 2022-10-07 09:30:06 +09:00
MITSUNARI Shigeo
2f7fb0220f modify gen.cpp for AVX-NE-CONVERT/AVX-VNNI-INT8/AMX-FP16 2022-10-07 09:28:12 +09:00
MITSUNARI Shigeo
6b75196597 add serialize 2022-09-15 09:02:54 +09:00
MITSUNARI Shigeo
553246c164 the version format has changed from A.BC(D) to A.BC(.D) 2022-06-03 09:48:24 +09:00
MITSUNARI Shigeo
72d1ac1183 add movdir64b 2022-05-12 10:51:23 +09:00
MITSUNARI Shigeo
379f8bf376 add movdiri 2022-05-12 09:56:15 +09:00
MITSUNARI Shigeo
a84ddc12dd support cldemote 2022-05-11 17:01:10 +09:00
MITSUNARI Shigeo
3a6cc626e8 add clwb 2022-05-11 16:02:49 +09:00
MITSUNARI Shigeo
a220fd69a2 add umwait 2022-04-05 15:08:12 +09:00
MITSUNARI Shigeo
64ec053e61 add umonitor 2022-04-05 14:56:52 +09:00
MITSUNARI Shigeo
764d54f6fa add tpause 2022-04-05 14:17:44 +09:00
MITSUNARI Shigeo
08f11817c4 supprt retf 2021-12-14 12:23:07 +09:00
MITSUNARI Shigeo
3162eb16f2 add test of hlt 2021-12-09 16:30:19 +09:00
MITSUNARI Shigeo
cfc03cb8f9 unify T_66, T_F3, T_F2 flags 2021-09-14 14:10:41 +09:00
MITSUNARI Shigeo
34abda5c5f extend vcvtps2ph 2021-09-14 09:31:53 +09:00
MITSUNARI Shigeo
16d18b1d46 fix v{add,sub,mul,...}{sd,ss} to support T_rd_sae etc. 2021-09-03 11:11:14 +09:00
MITSUNARI Shigeo
5df23d2630 move FP16 to AVX-512 2021-09-03 08:54:34 +09:00
MITSUNARI Shigeo
d5c7336f84 fix disp scaling of v{add,sub,mul,div,max,min}sh 2021-09-02 17:07:03 +09:00
MITSUNARI Shigeo
2c4b6ac163 add v{add,sub,mul,div,min,max}{ph,sh} 2021-09-02 15:55:18 +09:00
MITSUNARI Shigeo
a34850b2df add endbr32 and endbr64 2021-05-10 09:22:26 +09:00
MITSUNARI Shigeo
f85b1100b5 refactor vnni 2020-10-19 15:45:26 +09:00
MITSUNARI Shigeo
bb967ae752 replace uint32 with uint32_t etc. 2020-09-08 15:14:18 +09:00
MITSUNARI Shigeo
0fdffc6b90 XBYAK_NOEXCEPTION for -fno-exceptions 2020-07-20 18:24:34 +09:00
MITSUNARI Shigeo
c6737d14bf mov amx insts from avx512 2020-06-30 18:15:43 +09:00
Masaki Ota @MagurosanTeam
08b8b1baf0 Support AMD Zen New Instructions. 2019-09-23 12:04:36 +09:00
MITSUNARI Shigeo
72b4e95dab add lds/lss/les/lfs/lgs 2019-09-10 20:46:17 +09:00