Commit graph

88 commits

Author SHA1 Message Date
Jean-Marc Valin
ea8fbf46d5 Simplifying PLC switching to have an overlap of 2.5 ms too 2011-03-18 16:42:42 -04:00
Jean-Marc Valin
c983bb471a Minor code simplifications 2011-03-18 16:35:40 -04:00
Jean-Marc Valin
eed33090eb Minor redundant frame fixes 2011-03-18 16:29:15 -04:00
Jean-Marc Valin
f2c8e5dfee CELT update
With minor fixes
2011-03-18 15:49:18 -04:00
Jean-Marc Valin
617fcd2cf0 Fixes a few PLC/DTX bugs due to the recent decode API change 2011-03-16 22:11:53 -04:00
Jean-Marc Valin
ac768f3363 More error handling 2011-03-14 11:44:16 -04:00
Jean-Marc Valin
71877da4eb Error handling 2011-03-14 06:45:17 -04:00
Jean-Marc Valin
a7d31b7b15 Code for handling multiple frames per packet
Barely tested
2011-03-13 21:29:36 -04:00
Jean-Marc Valin
0fe4078b30 Adding some packet parsing code 2011-03-13 12:41:08 -04:00
Jean-Marc Valin
8ea67049c2 Disable newly introduced CELT signalling 2011-03-11 17:49:10 -05:00
Jean-Marc Valin
edaf788084 Updating the build of the draft and adding fixed-point support 2011-03-09 11:42:15 -05:00
Jean-Marc Valin
955f94c21a Automatic bandwidth selection 2011-03-08 22:12:43 -05:00
Jean-Marc Valin
f9bc460e36 Simple mode selection logic 2011-03-08 14:57:46 -05:00
Jean-Marc Valin
1b16fec484 Fixes a few issues with PLC-based mode switching 2011-03-07 23:53:53 -05:00
Jean-Marc Valin
0c0c5f940a Support for glitchles mode switching
Uses a 5ms redundant CELT frame embedded into the SILK or hybrid
packet to handle the switching. It's still possible to use the
PLC-based method when no redundant packet is included.
2011-03-07 20:54:33 -05:00
Jean-Marc Valin
a93f501cfa Fix PLC-based mode transition code. 2011-03-03 15:50:08 -05:00
Jean-Marc Valin
e2a09db92b Implementing decoder-side support for redundant mode switching (bemasc's idea) 2011-03-02 17:54:43 -05:00
Jean-Marc Valin
d41c028d69 Revert de32a5bf61
Moves all the delay compensation back into the encoder only
2011-03-02 15:43:31 -05:00
Jean-Marc Valin
de32a5bf61 Splitting the resampler buffering between encode and decode 2011-02-21 14:05:10 -05:00
Jean-Marc Valin
ca869b2ee4 Makes sure there's a PLC-only region in the mode transition 2011-02-16 00:41:04 -05:00
Jean-Marc Valin
73870719a2 Fixes infinite loop for frame size <= 5 ms 2011-02-15 20:10:40 -05:00
Jean-Marc Valin
606250ab7f Improved transitions between the different modes
Uses the PLC to prevent glitches
2011-02-15 14:31:21 -05:00
Koen Vos
71e10e2ef9 CELT/Hybrid fix for in-band FEC. 2011-02-14 21:51:35 -05:00
Koen Vos
1e1562c121 Update for in-band FEC 2011-02-14 15:04:59 -05:00
Jean-Marc Valin
5d56fc78b0 Relicensing to simplified (2-clause) BSD license 2011-02-10 21:42:37 -05:00
Jean-Marc Valin
2c8b29806b Better handling of the bandwidth 2011-02-04 00:38:50 -05:00
Timothy B. Terriberry
a1dd0fcf93 Update Opus range coder due to CELT refactoring.
The byte buffer is now part of the range coder struct itself, and
 rangeenc.c and rangedec.c have gone away.
2011-02-03 22:32:27 -05:00
Koen Vos
8f67b20a8f Testing the range coder final state 2011-02-03 09:31:12 -05:00
Jean-Marc Valin
44cbe6ea0d PLC fix 2011-02-02 09:39:30 -05:00
Jean-Marc Valin
a70729c0b4 Koen's decoder updates 2011-01-31 18:25:47 -05:00
Jean-Marc Valin
53fb0f775e Handling auto-detecting of frame size in decoder 2011-01-31 15:56:38 -05:00
Jean-Marc Valin
01b15eb259 Fixes resampling in CELT-only mode 2011-01-31 13:42:57 -05:00
Jean-Marc Valin
b386458fa3 Got stereo support to work in CELT-only mode 2011-01-31 12:41:49 -05:00
Jean-Marc Valin
eeca568211 More stereo work 2011-01-31 11:53:28 -05:00
Jean-Marc Valin
3ce277ca1f Some initial work on stereo support (not complete) 2011-01-31 11:34:57 -05:00
Jean-Marc Valin
e6f53b7303 Updated to CELT's new API 2011-01-30 23:44:51 -05:00
Jean-Marc Valin
b5be826131 Updated to follow changes in SILK API 2010-11-12 06:47:46 +08:00
Jean-Marc Valin
05dd36a1b3 API renamed to Opus 2010-10-18 12:50:49 -04:00
Renamed from src/harmony_decoder.c (Browse further)