Also #error if RTCD is enabled without a detection method, like Arm.
A number of SILK functions also still used the lookup tables, even
when RTCD was disabled.
Fix those, too.
Enable x86 intrinsics when building in floating-point mode.
Support SSE as an arch value.
Use RTCD to conditionally enable existing floating-point Celt SSE code.
Call functions directly (without RTCD) when their architecture can be presumed.
Use SSE4.1 intrinsics optimized code for Silk even in floating-point mode.
Actually try to compile intrinsics rather than using the output of --help.
Allow caller of configure script to set custom compiler options to enable intrinsics.
Detect when intrinsics are always available, without needing special compiler options.
Make naming of #defines for detected intrinsics support more systematic.
Optimize celt_pitch_xcorr function (for floating point)
using ARM NEON intrinsics for SoCs that have NEON VFP unit.
To enable this optimization, use --enable-intrinsics
configure option.
Compile time and runtime checks are also supported to make sure
this optimization is only enabled when the compiler supports
NEON intrinsics.
Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
1. Only for fixed point on x86 platform (32bit and 64bit, uses SIMD
intrinsics up to SSE4.2)
2. Use "configure --enable-fixed-point --enable-intrinsics" to enable
optimization, default is disabled.
3. Official test cases are verified and passed.
Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
Newer versions of MSVC are unhappy with the strategy of the build
environment redefining "inline" (even though they don't support the
actual keyword). Instead we define OPUS_INLINE to the right thing
in opus_defines.h.
This is the same approach we use for restrict.
Run-time CPU detection (RTCD) is enabled by default if target platform support
it.
It can be disable at compile time with --disable-rtcd option.
Add RTCD support for ARM architecture.
Thanks to Timothy B. Terriberry for help and code review
Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
