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Only build platform RTCD sources when enabled.

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To avoid issues with empty compilation units.
This commit is contained in:
Timothy B. Terriberry 2022-07-06 15:23:12 -07:00
parent 71fb707875
commit 0808841125
No known key found for this signature in database
GPG key ID: 5A1149C19C699E4F
8 changed files with 52 additions and 14 deletions
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8
CMakeLists.txt
View file

@ -381,6 +381,8 @@ if(NOT OPUS_DISABLE_INTRINSICS)
message(ERROR "Runtime cpu capability detection is enabled while CPU_INFO is not supported")
endif()
endif()
add_sources_group(opus celt ${celt_sources_x86_rtcd})
add_sources_group(opus silk ${silk_sources_x86_rtcd})
endif()
if(SSE1_SUPPORTED)
@ -465,15 +467,13 @@ if(NOT OPUS_DISABLE_INTRINSICS)
endif()
endif()
if(CMAKE_SYSTEM_PROCESSOR MATCHES "(arm|aarch64)")
add_sources_group(opus celt ${celt_sources_arm})
endif()
if(COMPILER_SUPPORT_NEON)
if(OPUS_MAY_HAVE_NEON)
if(RUNTIME_CPU_CAPABILITY_DETECTION)
message(STATUS "OPUS_MAY_HAVE_NEON enabling runtime detection")
target_compile_definitions(opus PRIVATE OPUS_HAVE_RTCD)
add_sources_group(opus celt ${celt_sources_arm_rtcd})
add_sources_group(opus silk ${silk_sources_arm_rtcd})
else()
message(ERROR "Runtime cpu capability detection needed for MAY_HAVE_NEON")
endif()

12
Makefile.am
View file

@ -36,6 +36,11 @@ else
OPUS_SOURCES += $(OPUS_SOURCES_FLOAT)
endif
if CPU_X86
if HAVE_RTCD
CELT_SOURCES += $(CELT_SOURCES_X86_RTCD)
SILK_SOURCES += $(SILK_SOURCES_X86_RTCD)
endif
if HAVE_SSE
CELT_SOURCES += $(CELT_SOURCES_SSE)
endif
@ -45,10 +50,13 @@ endif
if HAVE_SSE4_1
CELT_SOURCES += $(CELT_SOURCES_SSE4_1)
endif
endif
if CPU_ARM
CELT_SOURCES += $(CELT_SOURCES_ARM)
SILK_SOURCES += $(SILK_SOURCES_ARM)
if HAVE_RTCD
CELT_SOURCES += $(CELT_SOURCES_ARM_RTCD)
SILK_SOURCES += $(SILK_SOURCES_ARM_RTCD)
endif
if HAVE_ARM_NEON_INTR
CELT_SOURCES += $(CELT_SOURCES_ARM_NEON_INTR)

8
celt/meson.build
View file

@ -10,6 +10,10 @@ celt_neon_intr_sources = sources['CELT_SOURCES_ARM_NEON_INTR']
celt_static_libs = []
if host_cpu_family in ['x86', 'x86_64'] and opus_conf.has('OPUS_HAVE_RTCD')
celt_sources += sources['CELT_SOURCES_X86_RTCD']
endif
foreach intr_name : ['sse', 'sse2', 'sse4_1', 'neon_intr']
have_intr = get_variable('have_' + intr_name)
if not have_intr
@ -30,7 +34,9 @@ if (intrinsics_support.length() + asm_optimization.length() + inline_optimizatio
endif
if host_cpu_family in ['arm', 'aarch64'] and have_arm_intrinsics_or_asm
celt_sources += sources['CELT_SOURCES_ARM']
if opus_conf.has('OPUS_HAVE_RTCD')
celt_sources += sources['CELT_SOURCES_ARM_RTCD']
endif
if have_arm_ne10
celt_sources += sources['CELT_SOURCES_ARM_NE10']
endif

8
celt_sources.mk
View file

@ -18,9 +18,11 @@ celt/quant_bands.c \
celt/rate.c \
celt/vq.c
CELT_SOURCES_SSE = \
CELT_SOURCES_X86_RTCD = \
celt/x86/x86cpu.c \
celt/x86/x86_celt_map.c \
celt/x86/x86_celt_map.c
CELT_SOURCES_SSE = \
celt/x86/pitch_sse.c
CELT_SOURCES_SSE2 = \
@ -31,7 +33,7 @@ CELT_SOURCES_SSE4_1 = \
celt/x86/celt_lpc_sse4_1.c \
celt/x86/pitch_sse4_1.c
CELT_SOURCES_ARM = \
CELT_SOURCES_ARM_RTCD = \
celt/arm/armcpu.c \
celt/arm/arm_celt_map.c

5
cmake/OpusSources.cmake
View file

@ -9,9 +9,11 @@ get_opus_sources(SILK_HEAD silk_headers.mk silk_headers)
get_opus_sources(SILK_SOURCES silk_sources.mk silk_sources)
get_opus_sources(SILK_SOURCES_FLOAT silk_sources.mk silk_sources_float)
get_opus_sources(SILK_SOURCES_FIXED silk_sources.mk silk_sources_fixed)
get_opus_sources(SILK_SOURCES_X86_RTCD silk_sources.mk silk_sources_x86_rtcd)
get_opus_sources(SILK_SOURCES_SSE4_1 silk_sources.mk silk_sources_sse4_1)
get_opus_sources(SILK_SOURCES_FIXED_SSE4_1 silk_sources.mk
silk_sources_fixed_sse4_1)
get_opus_sources(SILK_SOURCES_ARM_RTCD silk_sources.mk silk_sources_arm_rtcd)
get_opus_sources(SILK_SOURCES_ARM_NEON_INTR silk_sources.mk
silk_sources_arm_neon_intr)
get_opus_sources(SILK_SOURCES_FIXED_ARM_NEON_INTR silk_sources.mk
@ -23,10 +25,11 @@ get_opus_sources(OPUS_SOURCES_FLOAT opus_sources.mk opus_sources_float)
get_opus_sources(CELT_HEAD celt_headers.mk celt_headers)
get_opus_sources(CELT_SOURCES celt_sources.mk celt_sources)
get_opus_sources(CELT_SOURCES_X86_RTCD celt_sources.mk celt_sources_x86_rtcd)
get_opus_sources(CELT_SOURCES_SSE celt_sources.mk celt_sources_sse)
get_opus_sources(CELT_SOURCES_SSE2 celt_sources.mk celt_sources_sse2)
get_opus_sources(CELT_SOURCES_SSE4_1 celt_sources.mk celt_sources_sse4_1)
get_opus_sources(CELT_SOURCES_ARM celt_sources.mk celt_sources_arm)
get_opus_sources(CELT_SOURCES_ARM_RTCD celt_sources.mk celt_sources_arm_rtcd)
get_opus_sources(CELT_SOURCES_ARM_ASM celt_sources.mk celt_sources_arm_asm)
get_opus_sources(CELT_AM_SOURCES_ARM_ASM celt_sources.mk
celt_am_sources_arm_asm)

5
configure.ac
View file

@ -195,6 +195,7 @@ AC_ARG_ENABLE([intrinsics],
rtcd_support=no
cpu_arm=no
cpu_x86=no
AS_IF([test x"${enable_asm}" = x"yes"],[
inline_optimization="No inline ASM for your platform, please send patches"
@ -535,6 +536,7 @@ AS_IF([test x"$enable_intrinsics" = x"yes"],[
],
[i?86|x86_64],
[
cpu_x86=yes
OPUS_CHECK_INTRINSICS(
[SSE],
[$X86_SSE_CFLAGS],
@ -744,6 +746,7 @@ AM_CONDITIONAL([HAVE_ARM_NEON_INTR],
[test x"$OPUS_ARM_MAY_HAVE_NEON_INTR" = x"1"])
AM_CONDITIONAL([HAVE_ARM_NE10],
[test x"$HAVE_ARM_NE10" = x"1"])
AM_CONDITIONAL([CPU_X86], [test "$cpu_x86" = "yes"])
AM_CONDITIONAL([HAVE_SSE],
[test x"$OPUS_X86_MAY_HAVE_SSE" = x"1"])
AM_CONDITIONAL([HAVE_SSE2],
@ -753,6 +756,8 @@ AM_CONDITIONAL([HAVE_SSE4_1],
AM_CONDITIONAL([HAVE_AVX],
[test x"$OPUS_X86_MAY_HAVE_AVX" = x"1"])
AM_CONDITIONAL([HAVE_RTCD],
[test x"$enable_rtcd" = x"yes" -a x"$rtcd_support" != x"no"])
AS_IF([test x"$enable_rtcd" = x"yes"],[
AS_IF([test x"$rtcd_support" != x"no"],[
AC_DEFINE([OPUS_HAVE_RTCD], [1],

10
silk/meson.build
View file

@ -21,6 +21,16 @@ endif
silk_includes = [opus_includes, include_directories('float', 'fixed')]
silk_static_libs = []
if host_cpu_family in ['x86', 'x86_64'] and opus_conf.has('OPUS_HAVE_RTCD')
silk_sources += sources['SILK_SOURCES_X86_RTCD']
endif
if host_cpu_family in ['arm', 'aarch64'] and have_arm_intrinsics_or_asm
if opus_conf.has('OPUS_HAVE_RTCD')
silk_sources += sources['SILK_SOURCES_ARM_RTCD']
endif
endif
foreach intr_name : ['sse4_1', 'neon_intr']
have_intr = get_variable('have_' + intr_name)
if not have_intr

10
silk_sources.mk
View file

@ -77,15 +77,19 @@ silk/stereo_find_predictor.c \
silk/stereo_quant_pred.c \
silk/LPC_fit.c
SILK_SOURCES_SSE4_1 = \
SILK_SOURCES_X86_RTCD = \
silk/x86/x86_silk_map.c
SILK_SOURCES_SSE4_1 = \
silk/x86/NSQ_sse4_1.c \
silk/x86/NSQ_del_dec_sse4_1.c \
silk/x86/x86_silk_map.c \
silk/x86/VAD_sse4_1.c \
silk/x86/VQ_WMat_EC_sse4_1.c
SILK_SOURCES_ARM_RTCD = \
silk/arm/arm_silk_map.c
SILK_SOURCES_ARM_NEON_INTR = \
silk/arm/arm_silk_map.c \
silk/arm/biquad_alt_neon_intr.c \
silk/arm/LPC_inv_pred_gain_neon_intr.c \
silk/arm/NSQ_del_dec_neon_intr.c \