GPU: Make use of RegisterSet.
This commit is contained in:
Tony Wasserka
parent
357d893b26
commit
75775e9ef4
4 changed files with 225 additions and 350 deletions
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@ -15,38 +15,48 @@
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namespace GPU {
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Registers g_regs;
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RegisterSet<u32, Regs> g_regs;
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u64 g_last_ticks = 0; ///< Last CPU ticks
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/**
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* Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
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* @param
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* @param
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*/
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void SetFramebufferLocation(const FramebufferLocation mode) {
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switch (mode) {
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case FRAMEBUFFER_LOCATION_FCRAM:
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g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1;
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g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2;
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g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1;
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g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2;
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g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1;
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//g_regs.framebuffer_sub_left_2 = unknown;
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g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2;
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//g_regs.framebufferr_sub_right_2 = unknown;
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{
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auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
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auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
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framebuffer_top.data.address_left1 = PADDR_TOP_LEFT_FRAME1;
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framebuffer_top.data.address_left2 = PADDR_TOP_LEFT_FRAME2;
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framebuffer_top.data.address_right1 = PADDR_TOP_RIGHT_FRAME1;
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framebuffer_top.data.address_right2 = PADDR_TOP_RIGHT_FRAME2;
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framebuffer_sub.data.address_left1 = PADDR_SUB_FRAME1;
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//framebuffer_sub.data.address_left2 = unknown;
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framebuffer_sub.data.address_right1 = PADDR_SUB_FRAME2;
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//framebuffer_sub.data.address_right2 = unknown;
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break;
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}
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case FRAMEBUFFER_LOCATION_VRAM:
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g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1;
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g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2;
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g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
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g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
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g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1;
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//g_regs.framebuffer_sub_left_2 = unknown;
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g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2;
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//g_regs.framebufferr_sub_right_2 = unknown;
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{
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auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
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auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
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framebuffer_top.data.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1;
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framebuffer_top.data.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2;
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framebuffer_top.data.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
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framebuffer_top.data.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
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framebuffer_sub.data.address_left1 = PADDR_VRAM_SUB_FRAME1;
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//framebuffer_sub.data.address_left2 = unknown;
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framebuffer_sub.data.address_right1 = PADDR_VRAM_SUB_FRAME2;
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//framebuffer_sub.data.address_right2 = unknown;
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break;
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}
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}
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}
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/**
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@ -87,219 +97,73 @@ const u8* GetFramebufferPointer(const u32 address) {
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}
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template <typename T>
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inline void Read(T &var, const u32 addr) {
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switch (addr) {
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case Registers::MemoryFillStart1:
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case Registers::MemoryFillStart2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start;
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break;
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inline void Read(T &var, const u32 raw_addr) {
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u32 addr = raw_addr - 0x1EF00000;
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int index = addr / 4;
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case Registers::MemoryFillEnd1:
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case Registers::MemoryFillEnd2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end;
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break;
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case Registers::MemoryFillSize1:
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case Registers::MemoryFillSize2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size;
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break;
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case Registers::MemoryFillValue1:
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case Registers::MemoryFillValue2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value;
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break;
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case Registers::FramebufferTopSize:
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var = g_regs.top_framebuffer.size;
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break;
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case Registers::FramebufferTopLeft1:
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var = g_regs.framebuffer_top_left_1;
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break;
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case Registers::FramebufferTopLeft2:
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var = g_regs.framebuffer_top_left_2;
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break;
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case Registers::FramebufferTopFormat:
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var = g_regs.top_framebuffer.format;
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break;
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case Registers::FramebufferTopSwapBuffers:
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var = g_regs.top_framebuffer.active_fb;
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break;
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case Registers::FramebufferTopStride:
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var = g_regs.top_framebuffer.stride;
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break;
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case Registers::FramebufferTopRight1:
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var = g_regs.framebuffer_top_right_1;
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break;
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case Registers::FramebufferTopRight2:
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var = g_regs.framebuffer_top_right_2;
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break;
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case Registers::FramebufferSubSize:
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var = g_regs.sub_framebuffer.size;
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break;
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case Registers::FramebufferSubLeft1:
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var = g_regs.framebuffer_sub_left_1;
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break;
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case Registers::FramebufferSubRight1:
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var = g_regs.framebuffer_sub_right_1;
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break;
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case Registers::FramebufferSubFormat:
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var = g_regs.sub_framebuffer.format;
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break;
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case Registers::FramebufferSubSwapBuffers:
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var = g_regs.sub_framebuffer.active_fb;
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break;
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case Registers::FramebufferSubStride:
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var = g_regs.sub_framebuffer.stride;
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break;
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case Registers::FramebufferSubLeft2:
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var = g_regs.framebuffer_sub_left_2;
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break;
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case Registers::FramebufferSubRight2:
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var = g_regs.framebuffer_sub_right_2;
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break;
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case Registers::DisplayInputBufferAddr:
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var = g_regs.display_transfer.input_address;
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break;
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case Registers::DisplayOutputBufferAddr:
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var = g_regs.display_transfer.output_address;
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break;
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case Registers::DisplayOutputBufferSize:
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var = g_regs.display_transfer.output_size;
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break;
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case Registers::DisplayInputBufferSize:
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var = g_regs.display_transfer.input_size;
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break;
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case Registers::DisplayTransferFlags:
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var = g_regs.display_transfer.flags;
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break;
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// Not sure if this is supposed to be readable
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case Registers::DisplayTriggerTransfer:
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var = g_regs.display_transfer.trigger;
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break;
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case Registers::CommandListSize:
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var = g_regs.command_list_size;
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break;
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case Registers::CommandListAddress:
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var = g_regs.command_list_address;
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break;
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case Registers::ProcessCommandList:
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var = g_regs.command_processing_enabled;
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break;
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default:
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// Reads other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
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{
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ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
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break;
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return;
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}
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var = g_regs[static_cast<Regs::Id>(addr / 4)];
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}
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template <typename T>
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inline void Write(u32 addr, const T data) {
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switch (static_cast<Registers::Id>(addr)) {
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case Registers::MemoryFillStart1:
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case Registers::MemoryFillStart2:
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g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data;
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break;
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addr -= 0x1EF00000;
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int index = addr / 4;
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case Registers::MemoryFillEnd1:
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case Registers::MemoryFillEnd2:
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g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data;
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break;
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case Registers::MemoryFillSize1:
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case Registers::MemoryFillSize2:
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g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data;
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break;
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case Registers::MemoryFillValue1:
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case Registers::MemoryFillValue2:
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// Writes other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
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{
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Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10];
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config.value = data;
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ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
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return;
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}
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g_regs[static_cast<Regs::Id>(index)] = data;
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switch (static_cast<Regs::Id>(index)) {
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// Memory fills are triggered once the fill value is written.
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// NOTE: This is not verified.
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case Regs::MemoryFill + 3:
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case Regs::MemoryFill + 7:
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{
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const auto& config = g_regs.Get<Regs::MemoryFill>(static_cast<Regs::Id>(index - 3));
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// TODO: Not sure if this check should be done at GSP level instead
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if (config.address_start) {
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if (config.data.address_start) {
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// TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
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u32* start = (u32*)Memory::GetPointer(config.GetStartAddress());
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u32* end = (u32*)Memory::GetPointer(config.GetEndAddress());
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u32* start = (u32*)Memory::GetPointer(config.data.GetStartAddress());
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u32* end = (u32*)Memory::GetPointer(config.data.GetEndAddress());
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for (u32* ptr = start; ptr < end; ++ptr)
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*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
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*ptr = bswap32(config.data.value); // TODO: This is just a workaround to missing framebuffer format emulation
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DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress());
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DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.data.GetStartAddress(), config.data.GetEndAddress());
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}
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break;
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}
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// TODO: Framebuffer registers!!
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case Registers::FramebufferTopSwapBuffers:
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g_regs.top_framebuffer.active_fb = data;
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// TODO: Not sure if this should only be done upon a change!
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break;
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case Regs::DisplayTransfer + 6:
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{
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const auto& config = g_regs.Get<Regs::DisplayTransfer>();
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if (config.data.trigger & 1) {
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u8* source_pointer = Memory::GetPointer(config.data.GetPhysicalInputAddress());
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u8* dest_pointer = Memory::GetPointer(config.data.GetPhysicalOutputAddress());
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case Registers::FramebufferSubSwapBuffers:
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g_regs.sub_framebuffer.active_fb = data;
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// TODO: Not sure if this should only be done upon a change!
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break;
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case Registers::DisplayInputBufferAddr:
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g_regs.display_transfer.input_address = data;
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break;
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case Registers::DisplayOutputBufferAddr:
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g_regs.display_transfer.output_address = data;
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break;
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case Registers::DisplayOutputBufferSize:
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g_regs.display_transfer.output_size = data;
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break;
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case Registers::DisplayInputBufferSize:
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g_regs.display_transfer.input_size = data;
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break;
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case Registers::DisplayTransferFlags:
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g_regs.display_transfer.flags = data;
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break;
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case Registers::DisplayTriggerTransfer:
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g_regs.display_transfer.trigger = data;
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if (g_regs.display_transfer.trigger & 1) {
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u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress());
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u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress());
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for (int y = 0; y < g_regs.display_transfer.output_height; ++y) {
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for (int y = 0; y < config.data.output_height; ++y) {
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// TODO: Why does the register seem to hold twice the framebuffer width?
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for (int x = 0; x < g_regs.display_transfer.output_width / 2; ++x) {
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for (int x = 0; x < config.data.output_width / 2; ++x) {
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int source[4] = { 0, 0, 0, 0}; // rgba;
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switch (g_regs.display_transfer.input_format) {
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case Registers::FramebufferFormat::RGBA8:
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switch (config.data.input_format) {
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case Regs::FramebufferFormat::RGBA8:
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{
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// TODO: Most likely got the component order messed up.
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u8* srcptr = source_pointer + x * 4 + y * g_regs.display_transfer.input_width * 4 / 2;
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u8* srcptr = source_pointer + x * 4 + y * config.data.input_width * 4 / 2;
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source[0] = srcptr[0]; // blue
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source[1] = srcptr[1]; // green
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source[2] = srcptr[2]; // red
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@ -308,15 +172,15 @@ inline void Write(u32 addr, const T data) {
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}
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default:
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ERROR_LOG(GPU, "Unknown source framebuffer format %x", (int)g_regs.display_transfer.input_format.Value());
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ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.data.input_format.Value());
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break;
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}
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switch (g_regs.display_transfer.output_format) {
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/*case Registers::FramebufferFormat::RGBA8:
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switch (config.data.output_format) {
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/*case Regs::FramebufferFormat::RGBA8:
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{
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// TODO: Untested
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u8* dstptr = (u32*)(dest_pointer + x * 4 + y * g_regs.display_transfer.output_width * 4);
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u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.data.output_width * 4);
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dstptr[0] = source[0];
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dstptr[1] = source[1];
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dstptr[2] = source[2];
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@ -324,9 +188,9 @@ inline void Write(u32 addr, const T data) {
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break;
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}*/
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case Registers::FramebufferFormat::RGB8:
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case Regs::FramebufferFormat::RGB8:
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{
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u8* dstptr = dest_pointer + x * 3 + y * g_regs.display_transfer.output_width * 3 / 2;
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u8* dstptr = dest_pointer + x * 3 + y * config.data.output_width * 3 / 2;
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dstptr[0] = source[0]; // blue
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dstptr[1] = source[1]; // green
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dstptr[2] = source[2]; // red
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@ -334,40 +198,34 @@ inline void Write(u32 addr, const T data) {
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}
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default:
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ERROR_LOG(GPU, "Unknown destination framebuffer format %x", static_cast<int>(g_regs.display_transfer.output_format.Value()));
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ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.data.output_format.Value());
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break;
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}
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}
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}
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DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x",
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g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4,
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g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height,
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g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height,
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(int)g_regs.display_transfer.output_format.Value());
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config.data.output_height * config.data.output_width * 4,
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config.data.GetPhysicalInputAddress(), (int)config.data.input_width, (int)config.data.input_height,
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config.data.GetPhysicalOutputAddress(), (int)config.data.output_width, (int)config.data.output_height,
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config.data.output_format.Value());
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}
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break;
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}
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case Registers::CommandListSize:
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g_regs.command_list_size = data;
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break;
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case Registers::CommandListAddress:
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g_regs.command_list_address = data;
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break;
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case Registers::ProcessCommandList:
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g_regs.command_processing_enabled = data;
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if (g_regs.command_processing_enabled & 1)
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case Regs::CommandProcessor + 4:
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{
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const auto& config = g_regs.Get<Regs::CommandProcessor>();
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if (config.data.trigger & 1)
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{
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// u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3);
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ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3);
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// u32* buffer = (u32*)Memory::GetPointer(config.data.address << 3);
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ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.data.size, config.data.address << 3);
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// TODO: Process command list!
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}
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break;
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}
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default:
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ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
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break;
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}
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}
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@ -402,18 +260,20 @@ void Init() {
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// SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
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SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM);
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auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
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auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
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// TODO: Width should be 240 instead?
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||||
g_regs.top_framebuffer.width = 480;
|
||||
g_regs.top_framebuffer.height = 400;
|
||||
g_regs.top_framebuffer.stride = 480*3;
|
||||
g_regs.top_framebuffer.color_format = Registers::FramebufferFormat::RGB8;
|
||||
g_regs.top_framebuffer.active_fb = 0;
|
||||
framebuffer_top.data.width = 480;
|
||||
framebuffer_top.data.height = 400;
|
||||
framebuffer_top.data.stride = 480*3;
|
||||
framebuffer_top.data.color_format = Regs::FramebufferFormat::RGB8;
|
||||
framebuffer_top.data.active_fb = 0;
|
||||
|
||||
g_regs.sub_framebuffer.width = 480;
|
||||
g_regs.sub_framebuffer.height = 400;
|
||||
g_regs.sub_framebuffer.stride = 480*3;
|
||||
g_regs.sub_framebuffer.color_format = Registers::FramebufferFormat::RGB8;
|
||||
g_regs.sub_framebuffer.active_fb = 0;
|
||||
framebuffer_sub.data.width = 480;
|
||||
framebuffer_sub.data.height = 400;
|
||||
framebuffer_sub.data.stride = 480*3;
|
||||
framebuffer_sub.data.color_format = Regs::FramebufferFormat::RGB8;
|
||||
framebuffer_sub.data.active_fb = 0;
|
||||
|
||||
NOTICE_LOG(GPU, "initialized OK");
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue