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Implement LogicOP Workaround for Vulkan on AMD GPUs

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This fixes black sewers in Paper Mario: TTYD
Credit: Antique - [Sudachi] Dev (https://sudachi.emuplace.app/)
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JPikachu 2025-04-08 18:17:28 +01:00 • committed by GitHub
parent e59f7922a1
commit 08ac410558
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GPG key ID: B5690EEEBB952194
2 changed files with 40 additions and 2 deletions
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19
src/video_core/renderer_opengl/gl_rasterizer.cpp
View file

@ -1204,7 +1204,24 @@ void RasterizerOpenGL::SyncLogicOpState() {
} }
flags[Dirty::LogicOp] = false; flags[Dirty::LogicOp] = false;
const auto& regs = maxwell3d->regs; auto& regs = maxwell3d->regs;
if (device.IsAmd()) {
using namespace Tegra::Engines;
struct In {
const Maxwell3D::Regs::VertexAttribute::Type d;
In(Maxwell3D::Regs::VertexAttribute::Type n) : d(n) {}
bool operator()(Maxwell3D::Regs::VertexAttribute n) const {
return n.type == d;
}
};
bool has_float =
std::any_of(regs.vertex_attrib_format.begin(), regs.vertex_attrib_format.end(),
In(Maxwell3D::Regs::VertexAttribute::Type::Float));
regs.logic_op.enable = static_cast<u32>(!has_float);
}
if (regs.logic_op.enable) { if (regs.logic_op.enable) {
glEnable(GL_COLOR_LOGIC_OP); glEnable(GL_COLOR_LOGIC_OP);
glLogicOp(MaxwellToGL::LogicOp(regs.logic_op.op)); glLogicOp(MaxwellToGL::LogicOp(regs.logic_op.op));

21
src/video_core/renderer_vulkan/vk_rasterizer.cpp
View file

@ -952,6 +952,27 @@ void RasterizerVulkan::UpdateDynamicStates() {
UpdateDepthBiasEnable(regs); UpdateDepthBiasEnable(regs);
} }
if (device.IsExtExtendedDynamicState3EnablesSupported()) { if (device.IsExtExtendedDynamicState3EnablesSupported()) {
using namespace Tegra::Engines;
if (device.GetDriverID() == VkDriverIdKHR::VK_DRIVER_ID_AMD_OPEN_SOURCE
|| device.GetDriverID() == VkDriverIdKHR::VK_DRIVER_ID_AMD_PROPRIETARY) {
struct In {
const Maxwell3D::Regs::VertexAttribute::Type d;
In(Maxwell3D::Regs::VertexAttribute::Type n) : d(n) {}
bool operator()(Maxwell3D::Regs::VertexAttribute n) const {
return n.type == d;
}
};
auto has_float = std::any_of(
regs.vertex_attrib_format.begin(), regs.vertex_attrib_format.end(),
In(Maxwell3D::Regs::VertexAttribute::Type::Float));
if (regs.logic_op.enable)
regs.logic_op.enable = static_cast<u32>(!has_float);
UpdateLogicOpEnable(regs);
} else
UpdateLogicOpEnable(regs); UpdateLogicOpEnable(regs);
UpdateDepthClampEnable(regs); UpdateDepthClampEnable(regs);
} }