forked from eden-emu/eden
glsl: Fix "reg" allocing
based on glasm with some tweaks
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parent
eaff1030de
commit
64337f004d
10 changed files with 938 additions and 898 deletions
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@ -10,7 +10,7 @@
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#include "shader_recompiler/backend/glsl/reg_alloc.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#pragma optimize("", off)
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namespace Shader::Backend::GLSL {
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namespace {
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constexpr std::string_view SWIZZLE = "xyzw";
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@ -24,11 +24,7 @@ std::string Representation(Id id) {
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}
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const u32 num_elements{id.num_elements_minus_one + 1};
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const u32 index{static_cast<u32>(id.index)};
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if (num_elements == 4) {
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return fmt::format("R{}", index);
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} else {
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return fmt::format("R{}.{}", index, SWIZZLE.substr(id.base_element, num_elements));
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}
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return fmt::format("R{}", index);
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}
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std::string MakeImm(const IR::Value& value) {
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@ -56,7 +52,8 @@ std::string RegAlloc::Define(IR::Inst& inst, u32 num_elements, u32 alignment) {
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}
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std::string RegAlloc::Consume(const IR::Value& value) {
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return value.IsImmediate() ? MakeImm(value) : Consume(*value.Inst());
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const auto result = value.IsImmediate() ? MakeImm(value) : Consume(*value.InstRecursive());
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return result;
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}
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std::string RegAlloc::Consume(IR::Inst& inst) {
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@ -93,4 +90,30 @@ void RegAlloc::Free(Id id) {
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register_use[id.index] = false;
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}
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/*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::Identity:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastU32F32:
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case IR::Opcode::BitCastU64F64:
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case IR::Opcode::BitCastF16U16:
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case IR::Opcode::BitCastF32U32:
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case IR::Opcode::BitCastF64U64:
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return true;
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default:
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return false;
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}
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}
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/*static*/ IR::Inst& RegAlloc::AliasInst(IR::Inst& inst) {
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IR::Inst* it{&inst};
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while (IsAliased(*it)) {
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const IR::Value arg{it->Arg(0)};
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if (arg.IsImmediate()) {
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break;
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}
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it = arg.InstRecursive();
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}
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return *it;
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}
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} // namespace Shader::Backend::GLSL
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